Development of World’s First Practical technology for 20nm Generation LSI by TOSHIBA
Truly a significant development in the world of LSI, with the announcement of Toshiba that its has developed a groundbreaking technology for steep channel impurity distribution, a solution to a key problem for 20nm generation CMOS technology, a technology which paves the way to a future generation of LSI which fabricated with bulk CMOS technology which is the mainstream technology in today’s LSI. Through utilization of this technology three layers are being formed on the surface of the channel namely epitaxial silicon (Si), carbon-doped silicon (Si:C) as well as boron-doped Si:C, where the top epitaxial Si layer functions as a low resistance path for the electrons and the holes, the middle SI:C layer functions as a defensive layer in preventing impurity diffusion and the bottom layer boron-doped Si:C layer is responsible for suppressing the fixed charge which is caused b the Si:C layer formation. The new structure will result in boost in performance by 15 to 18% in comparison to the conventional channel structure. The new structure can be applied to both the nMOS and pMOS transistors to configure CMOS devices with a simple process that adds a few layer-forming steps. Toshiba’s new technology achieves the high performance 20nm generation process through optimization of impurity materials, device structure and process. The newly developed technology is an answer to what today’s bulk CMOS technology is facing which is the physical limitation of around 20nm, where problems such as degradation in electron mobility in the channel area and variation in threshold voltage will become apparent. Up to now, the industry’s answer to overcome this physical limitation was in employing new materials or device structures such as SOI wafers and a 3D gate structure, but these solutions bear with them new process steps requiring extra facility investment as well as lower productivity.
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