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Development of Low Power, Low Noise All-Digital Phase Lock Loop LSI by NEC

As demand for short distance radio communication for such systems as remote controllers, alarm systems and automatic meter reading is on the rise, one major concern that has preoccupied manufacturers of these systems is their power consumption, requiring these systems to have a longer battery life. At the same time, small and lightweight criteria for wireless devices imposed by the market demand forcing manufacturer to further reduce the battery, however, reduced battery size will translate to reduced total available energy. For such battery driven devices one way to extend the battery life is through intermittent operation through use of all digital PLL (Phase Lock Loop) offering a quick operations as well as their advantage in eliminating large on-chip passive filters. In comparison analog-based PLL does not constitute a good solution due to their long start-up time. Based on this requirement, NEC and NED Electronics developed a low-power low-noise all-digital phase lock loop (ADPLL) LSI targeted to be employed in midget wireless equipment yielding a long operation lifetime for small sized batteries.
The key building block of this newly developed ADPLL is the TDC (Time-to-Digital Converter), providing a high accuracy in time-domain signal processing with reduced power consumption. The new architecture in designing the ADPLL is based on a fine/coarse two-step phase comparison scheme which can greatly reduce the number of circuit elements that need to be powered in each timing comparison step, resulting in a fraction of the PLL circuit to be powered, requiring minimum time and other circuits are automatically shut down. In achieving low phase noise in this newly developed LSI NEC has added a random signal to the oscillator, which resulted in drastic suppression of undesired noise originating from digitally periodic control, making the LSI suitable for modern wireless systems, including Bluetooth, ZigBee , WiFi as well as WiMAX. The new LSI features a short lock-up time (recovery time from sleep mode) of 20 microseconds and low operation current of 8.1mA. The new LSI operates at low phase noise of -105 dBc/Hz within the frequency range of 2.1 GHz to 2.8 GHz, making the LSI to be compatible with a wide array of wireless systems.
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