Development of New SRAM Circuit Technologies for 40nm LSIs and Beyond by RENESAS
One of the major hurdles in miniaturization of SRAM circuits is increase of random variability, making the design of advance semiconductor devices more difficult, where SRAM is among the components that are most susceptible to the effects of this random variability. Several methods have been proposed to overcome this issue, including addition of multiple power control circuits for controlling individual SRAM power lines, word lines, and data lines, but these approaches will not result in reduction of overall area of devices merely due to introduction of large-sized power control circuits. To address this issue, Renesas Electronics, has successfully developed a new SRAM circuit technologies capable of reducing adverse impact of increased random variability in advanced LSI at 40nm level and beyond.
Among the key features of this newly developed technology is; Multi-step world line control technology for reducing the degradation of operating margin and Hierarchical SRAM technology for increasing speed and achieving smaller circuit area, by dividing up the bit lines so that each is connected to fewer tiny SRAM cells. Renesas used this new technology to manufacture 2 Mb SRAM prototype devices at 40nm CMOS process node with tiny SRAM cells of 0.248 square micrometers, achieving world’s highest level of bit density of 2.98 megabits per square millimeter. The new technology also has a potential to overcome issues related to random variability in characteristics in an effort to further reduction of power-supply voltage levels for ultra low-power applications.
The new technology will pay the way for manufacturing of reduced cost and lower power consumption advanced system LSIs.