Development of an Innovative New Design Methodology for achieving Higher Circuit Density and Shorter Development Time in 28nm SoC Devices
Fujitsu Semiconductor has announced the development of a new design methodology which will enable the manufacturer of 28nm SoC (System on Chip) to achieve higher circuit density and shorter development time. Utilizing the new method will increase the circuit density by 33% while reducing the time for final layout process to as little as one month. The new method will minimize “White Space” where no transistors are placed, allowing more circuits to fit in a chip. The new design will also take into consideration wiring routs and timing closure to optimize internal data buses.
Furthermore, the new method will automatically synthesizes the new list data for physical layout, without any needs for manually changing the logic design resulting in improved routability and ease of timing closure as well as reducing time for final layout process as well as higher density integration.